The present invention generally relates to a circuit for converting high DC voltage to low DC voltage and more particularly to a semiconductor integrated circuit.
Semiconductor integrated circuit devices are well known in the art. Typically, they are constructed in a semiconductor substrate and powered by an external DC power source. A typical externally supplied voltage is 3.3 volts. However, as the scale of integration increases and the dimensions of the critical components of the active elements within a circuit decreases due to increased shrinkage of the semiconductor integrated circuit, the voltage that can cause breakdown of the various components also decreases. Thus, these integrated circuits must be operated at a lower DC voltage.
Where the semiconductor integrated circuit components have shrunk such that the operating voltage is lowered to e.g. 1.8 volts, but the semiconductor integrated device must still fit in a xe2x80x9csocketxe2x80x9d designed to operate at 3.3 volts, a high DC voltage to low DC voltage converter circuit must be used to convert the externally supplied 3.3 volts to an internal DC voltage of 1.8 volts. Although high DC voltage to low DC voltage converters are well known in the art, they have shortcomings which are addressed by the circuit converter of the present invention.
Accordingly, in one non-limiting aspect of the present invention, a high DC voltage to low DC voltage circuit converter comprises a first NMOS transistor having a first terminal, a second terminal and a gate for controlling the flow of current between the first terminal and the second terminal. The first terminal is connected to the high DC voltage and the second terminal provides the converted low DC voltage. A resistor divider circuit has a first node, a middle node, and a second node. The first node is also connected to the high DC voltage. The middle node is connected to the gate of the first NMOS transistor. A plurality of serially connected NMOS transistors has a first end and a second end with the first end connected to the second node, and the second end connected to ground. Each of the plurality of serially connected NMOS transistors has a first terminal, a second terminal and a gate for controlling the flow of current between the first terminal and the second terminal. The first terminal of one NMOS transistor is connected to its gate and to a second terminal of an adjacent NMOS transistor.